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MITSUBISHI DIGITAL TV ICs
M65665SP/FP
PICTURE-IN-PICTURE SIGNAL PROCESSING DESCRIPTION
The M65665SP/FP is a PIP (Picture in Picture) signal processing LSI, whose sub-picture input is composite signal or component signals(Y /C or Y /U/V) f or NTSC, PAL-M, and PAL-N. The built-in f ield memory (168k-bit RAM) , V-chip data slicer and analog circuitries lead the high quality PIP sy stem low cost and small size.
APPLICATION
NTSC, PAL-M, PAL-N color TV
RECOMMENDED OPERATING CONDITIONS
Supply v oltage range ------------------------ 3.2 ~ 3.5 V Operating f requency ----------------------- 14.32 MHz Operating temperature ------------------------ 0 ~ 70 deg. Input v oltage (CMOS interf ace) "H" ----- VDD x 0.7 ~ VDD V "L" ----0 ~ VDD x 0.3 V Output current ( output buf f er ) ------------ 4 mA ( MAX ) Output load capacitance ---------------------- 20 pF ( MAX ) *1 Circuit current ----------------------------------mA
FEATURES
* * * * *
Internal V-chip data slicer (f or sub-picture) NOTICE: Connect a 0.1F or larger capacitor between VDD and VSS pins. Vertical f ilter f or sub-picture ( Y signal ) *1 : Include pin capacitance ( 7 pF ) Base band comb f ilter (2 Line) Single sub-picture ( selectable picture size : 1/9 , 1/16 ) Sub-picture processing specif ication ( 1/9 , 1/16 size) : Quantization bits Y , B-Y, R-Y : 7 bits Horizontal sampling 229 pixels (Y ), 57 pixels (B-Y , R-Y ) Vertical lines 69/ 52 lines * Frame ( sub-picture ) on/of f * Built-in analog circuits : Two 8-bit A/D conv erter (f or sub-picture signal) Three 8-bit D/A conv erters (f or Y , U and V of sub-picture) Sy nc-tip-clamp, VCXO,OSD switch ... etc.. Block diagram & Application examples * IIC BUS control ( parallel/serial control) : Shown next pages PIP on/of f , Frame on/of f ( programmable luma lev el), Sub-picture size ( 1/9, 1/16 ), PIP position ( f ree position ), Picture f reeze , Y delay adjustment, Chroma lev el, Tint, Black lev el, Contrast ...etc..
PIN CONFIGURATION (TOP VIEW)
SWM OSD_SEL SDAT A SCLK DVdd DVss BGPS SCK BGPM FSC TEST5 TESTEN SWMG RESET CSYNCS AVdd(ad) Vin(ad) Uin(ad) Vrb Yin(ad) Vrt
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
Y(R)OUT OSD_RIN AGndDA U(G)OUT OSD_GIN VZ V(B)OUT OSD_BIN VddDA VD HD AVss(vcxo) X'tal(P-N) X'tal(P-M) X'tal(NT ) BIAS Filter AVdd(vcxo) CVBSin(ad) AVss(ad) Cin(ad)
Outline 42 Pin SDIP Package (M65665SP) Outline 0.8mm pitch 42 Pin SOP Package (M65665FP)
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MITSUBISHI DIGITAL TV ICs
M65665SP/FP
PICTURE-IN-PICTURE SIGNAL PROCESSING
BLOCK DIAGRAM
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MITSUBISHI DIGITAL TV ICs
M65665SP/FP
PICTURE-IN-PICTURE SIGNAL PROCESSING
ABSOLUTE MAXIMUM RATINGS (VSS=0V) Sy m bol VDD3 VI VI VO IO PD Topr Tstg Limits Parameter Supply v oltage (3.3V) Input v oltage(except 5V input) Input v oltage(5V input) Output v oltage Output current
(*1)
Conditions Min. -0.3 -0.3 -0.3 -0.3 IOH = -4 -10 -50 Max. 4.2 VDD3+0.3 5.25 VDD3+0.3 IOL = 4 1200 70 125
Unit V V V V mA mW deg. deg.
Power dissipation Operating temperature Storage temperature
(*1) Output current per output terminal. But Pd limits all current.
TYPICAL CHARACTERISTICS
THERMAL DERATING (MAXIMUM RATING)
2000 1600 1200 800 400 0 0 25 50 7075 100 125
AMBIENT TEMPERATURE Ta (deg.)
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MITSUBISHI DIGITAL TV ICs
M65665SP/FP
PICTURE-IN-PICTURE SIGNAL PROCESSING
DC CHARACTERISTICS
(Ta = 25 deg. unless otherwise noted) Sy m bol VIL VIH IIH IIL VTVT+ VH IIH IIL VOL VOH IOL IOH IOZL IOZH CI CO CIO IDD Input pin capacitance Output pin capacitance Bidirectional pin capacitance Operating current 3.3V supply f = 1MHz, VDD = 0V Output leakage current H VDD = 3.6V, VO = 3.6V -10 7 7 7 140 CMOS output current Input current (5.0V CMOS interf ace) CMOS output v oltage Parameter Input v oltage (3.3V CMOS interf ace) Input current (3.3V CMOS interf ace) Input v oltage schmitt (5.0V CMOS interf ace) L H L H +
Hysteresis
(VSS=0V) Limits Min. Ty p. Max. 0.81 3.6 10 10 1.65 2.7 1.2 10 10 0.05 mA -2 10 10 15 15 15 mA pF A V A V A V
Condition VDD = 2.7V VDD = 3.6V VDD = 3.6V, VI = 0V VDD = 3.6V, VI = 3.6V 0 2.52 -10 -10 0.8 VDD = 3.3V 1.4 0.3 VDD = 3.6V, VI = 0V VDD = 3.6V, VI = 3.6V VDD = 3.3V, |IO| = 1A H L H L VDD = 3.3V, VOL = 0.4V VDD = 3.3V, VOH = 2.6V VDD = 3.6V, VO = 0V -100 -10 3.25 2 -10
Unit
L H L
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MITSUBISHI DIGITAL TV ICs
M65665SP/FP
PICTURE-IN-PICTURE SIGNAL PROCESSING
PIN DESCRIPTION
Name Pin No. SWM 1 OSD_SEL 2 SDATA 3 SCLK 4 DVdd1 5 DVss1 6 BGPS 7 SCK 8 BGPM 9 FSC 10 11 TEST5 TESTEN 12 SWMG 13 RESET 14 15 CSYNCS 16 AVdd (ADC) 17 VIN (ADC) UIN (ADC) 18 19 VRB Y IN (ADC) 20 21 VRT CIN 22 AVss (ADC) 23 24 CVBSIN AVdd (VCXO) 25 FILTER 26 27 BIAS X'tal (NTSC) 28 29 X'tal (PAL-M) X'tal (PAL-N) 30 31 AVss (VCXO) 32 HD 33 VD AVdd (DAC) 34 OSDBIN 35 36 VOUT VZ 37 38 OSDGIN 39 UOUT 40 AVss (sub) OSDRIN 41 YOUT 42
I/O Function CMOS output PIP switch output Output OSD select CMOS input CMOS I/O(5V)*1 I2C SDA input/output CMOS input(5V)*1 I2C SCL input Digital Vdd Vdd f or digital part Digital Vss Vss f or digital part Test output CMOS output Test input CMOS input Test output CMOS output Test input CMOS input Test input CMOS input Test input CMOS input CMOS input Power on reset input CMOS input Sub picture external C-sy nc input CMOS input Analog Vdd Vdd f or internal ADC Analog Sub picture V input of ADC Analog Sub picture U input of ADC Analog Low lev el ref erence v oltage output of ADC Analog Sub picture Y input of ADC High lev el ref erence v oltage output of ADC Analog Analog Sub picture C input of ADC Analog Vss Vss f or internal ADC Analog Sub picture CVBS input of ADC Analog Vdd Vdd f or VCXO VCXO f ilter v oltage connection Analog VXCO bias v oltage connection Analog Analog X'tal of N TSC connection Analog X'tal of PAL-M connection Analog X'tal of PAL-N connection Analog Vss Vss f or VCXO CMOS input(5V)*1 Main picture HD input CMOS input(5V)*1 MAIN picture VD input Analog Vdd Vdd f or DAC OSD input of B Analog Analog Sub picture V or B output Analog Voltage ref erence output of D AC OSD input of G Analog Sub picture U or G output Analog Vss f or DAC Analog Vss Analog OSD input of R Analog Sub picture Y or R output
Remarks
connect to GND connect to GND connect to GND connect to GND connect to Vdd
*1 ) (5V)means 5V I/F torelant
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MITSUBISHI DIGITAL TV ICs
M65665SP/FP
PICTURE-IN-PICTURE SIGNAL PROCESSING
Dig.
BASIC APPLICATION EXAMPLE < NTSC only application example >
Ana. 0.01 0.01
22 23 21 20 19 18 17
Digital +3.3V power supply Digital GND Analog +3.3V power supply Analog GND
Sub C(Y/C) input Sub CVBS and Y(Y/C) input
0.22 12K 0.66V(max) 1.0V(max) 0.033 5M 0.22 X1 12~ 36p 0 0.1
0.1
Sub Y(YUV) input
0.01
24 25 26
0.1 0.1
Sub U input Sub V input
15 pin input when CSYNC of sub picture is fed from external 3.3V 0V
27 28 29 30
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
X1 : 14.31818MHz
5V (3.3V recommended) 0V 5V (3.3V recommended) 0V
10K
10
31
Main HD input Main VD input
32 33 34 35
PIP V or B output
0.7V (typ) 0.01
36 37 38 39 40 41
PIP U or G output
IIC BUS Clock input IIC BUS DATA input /output
0.7V (typ)
PIP Y or R output PIP SW output
42
3.3V 0V
< NTSC / PAL-M / PAL-N application example >
0.01 0.01
22 23 21 20
Sub C(Y/C) input Sub CVBS and Y(Y/C) input
0.22 0.66V(max) 1.0V(max) 0.033 5M 0.22 X1 12K 0.1
0.1
19
Sub Y(YUV) input Sub U input Sub V input
15 pin input when CSYNC of sub picture is fed from external 3.3V 0V
24 25 26
0.01
18
0.1
17
0.1
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
27 28
X1 : 14.31818MHz X2 : 14.30244MHz X3 : 14.328MHz
5V (3.3V recommended) 0V 5V (3.3V recommended) 0V
12~ 36p 12~ 36p 12~ 36p X2
0
29 30 31
X3 0 0
10K
10
Main HD input Main VD input OSD B input PIP V or B output
0.7V (typ) 0.01
32 33 34 35
0.1
36 37 38
OSD G input PIP U or G output OSD R input
0.7V (typ) 3.3V 0V
0.1
39 40 41
IIC BUS Clock input IIC BUS DATA input /output OSD selection input
2 pin input level 3.3V
0.1
42
PIP Y or R output PIP SW output
0V
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MITSUBISHI DIGITAL TV ICs
M65665SP/FP
PICTURE-IN-PICTURE SIGNAL PROCESSING
M65665SP/FP TV SYSTEM BLOCK DIAGRAM

Composite Video Signal
Y Y/C Separation C
Y C Video Signal Processing M65665SP/FP
Y U V Matrix
R G B Def lection Unit HD VD Yoke
Y/C Separated Video Signal
Y C
CV/Y
Y PIP Signal U Processing V SWM
Y/U/V Component Video Signal
Y U V
Composite Video Signal
Y Y/C Separation C
Y R C Video Signal Processing M65665SP/FP G B Def lection Unit HD VD Yoke
Y/C Separated Video Signal
Y C
CV/Y
R G PIP Signal Processing B SWM
Y/U/V Component Video Signal
Y U V
OSD_RGB
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MITSUBISHI DIGITAL TV ICs
M65665SP/FP
PICTURE-IN-PICTURE SIGNAL PROCESSING
Internal register inf ormation (preliminary )
address
bit 00h <7> <6> <5> <4> <3> <2> <1> <0> 01h <7:0> 02h <7:0> 03h <7> <6:0> 04h <7> <6:0> 05h <7> <6> <5:0> 06h <7:6> <5:4> <3:0> <7:6> <5:0> <7:4> <3:0> <7:5> <4:0> <7> <6:4> <3:0> <7:4> <3:0> <7> <6> <5:4> <3> <2> <1:0>
sy m bol DISP SIZE_V SIZE_H WEN BGC BGCS FREE_RUN RVS VXA<7:0> HXA<7:0> DECODE CONTRAST<6:0> KILLER U_DAC<6:0> GRC YUVN_RGB_SEL TINT<5:0> EXT_SC_SEL<1:0> DCONT<1:0> HT<3:0> INPUT_SEL<1:0> BG_START<5:0> ADJ<3:0> YDL<3:0> BGBY <2:0> Y_OFFSET<4:0> VCHIP_ONLY BGRY<2:0> BGY <3:0> PEDESTV<3:0> PEDESTU<3:0> UV_FILTER_OFF SET_ACC SYSTEM_MODE<1:0> SET_SIZE SET_VCHIP SYNC_DELAY <1:0> YUV_COL<3:0>
Reset val. 1/9 ex.
0 0 0 0 0 0 0
1 0 0 1 0 0 0
0 20h 20h 0 0 32h 0 0 32h 1 0 0 00h 00h 0h 0h 0 0 Ah 2h 0Eh 2h 5h 0h 0Fh 0 0h Ch 0h 0h 0 0 0h 0 0 0 0h 0 0h 0h 0h 0 0 15h 0 0 0 0 0 0 0 1
remarks Sub picture display : [0] of f , [1] on Sub picture v ertical size : [0] 1/9, [1] 1/16 Sub picture horizontal size : [0] 1/9, [1] 1/16 Sub picture : [0] Still, [1] Mov ing Back ground display : [0] of f , [1] on Sub picture mute : [0] of f , [1] on VCXO oscilation : [0] Lock, [1] Free run HD/VD input s y nchronous mode selection : [0] sy nc., [1] asy nc. Sub picture v ertical position Sub picture horizontal position Sub picture color decoder reset : [1] reset Sub picture Y or R DAC output amplitude control Sub picture color killer : [0] enable, [1] disable Sub picture U or G DAC output amplitude control Frame display : [0] of f , [1] on PIP output mode selection : [0] YUV, [1] RGB Sub picture tint control Sub picture C-Sy nc sep. input selection : [0] Digital, [1] int. Auto slice [2] external (18 pin), [3] Int. analog Sub picture sy nc sep.threshold setting (analog/digital) Sub picture display timing adjust Sub picture input selection : [0] YC, [1] N.A., [2]CVBS, [3] YUV Sub picture BGP position setting Main/Sub switch delay control Sub picture Y/C delay adjust Back ground U lev el setting Sub picture Y bright control V-chip decode mode : [0] of f , [1] on Back ground V lev el setting Back ground Y lev el setting Sub picture V pedestal lev el (2's comp) Sub picture U pedestal lev el (2's comp) Sub picture U, V output f ilter : [0]on, [1]of f Address 0Dh, 0Eh setting mode : [0]def ault, [1] enable to set Sy stem : [0]NTSC , [1]PAL-M, [2]PAL-N, [3] N.A. Address 11h - 14h setting mode : [0]def ault, [1] enable to set Address 15h - 17h setting mode : [0]def ault , [1] enable to set Sub picture sy nc.delay control Sub picture color control parameter when YUV input Sub picture chroma : [0] x1, [1] x2 Sub picture killer on when its v ert. sy nc lost : [0] on, [1] of f f or test : 0 set only Internal chroma comb f ilter : [0] on : [1] of f Sub picture Y clamp time constant : [0] x2, [1] x1 Sub picture AFC time constant : [0] x2, [1] x1 Sub picture color decoder amplitude Sy stem automatic judgment : [0] of f , [1] on VCXO mode selection : [0] 1H based, [1] 2H based Main picture PAL-N : [0] enable, [1] disable Inv ert sub picture f ield def inition : [0] normal, [1] inv ert Inv ert main picture f ield def inition : [0] normal, [1] inv ert Vertical display m odewhen PAL-N input : [0] normal, [1] wide Main picture f ield f ix : [0] not f ix, [1]f ix Automatic 50/60Hz Judgment : [0] enable, [1] disable
07h 08h 09h 0Ah
0h 0 0h 0h 0h 0 0 0h 0 0 0 0h
0Bh 0Ch
0Dh <7:4> <3> <2> <1> <0> 0Eh <7> <6> <5:0> 0Fh <7> <6> <5> <4> <3> <2> <1> <0>
C_GAIN_SEL 0 0h WDOF_KILLER_ON EDGE_RES 0h 0h CVF 0 BITSEL 0 AFCBITSEL ACC_LEVEL<5:0> 0 AUTO_ENABLE BURST_CLOCK_MODE 0 PALN_DISABLE 0 INV_WFF 0 INV_RFF 0 VMODE 0 RFF_FIX 0 0 AUTO_RFF_FIX
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MITSUBISHI DIGITAL TV ICs
M65665SP/FP
PICTURE-IN-PICTURE SIGNAL PROCESSING
Internal register inf ormation (continuing) (preliminary )
address
bit 10h <7:6> <5:4> <3:0> 11h <7> <6:0> 12h <7:0> 13h <7:2> <1:0> 14h <7:6>
sy m bol NO_BST_LEVEL BW_DET_LEVEL PALRY<3:0> CROSS_SEL HYA<6:0> VYA<7:0> HX<5:0> HP<1:0> MVC<1:0> VXS<5:0> PLUS LINE_NUM<4:0> STB_DLY <7:0> L_LEVEL<7:0> EDGE_ON BGBY_EDGE<2:0> BGY _EDGE<3:0> BGRY_EDGE<2:0>
Reset val. 1/9 ex.
<5:0> 15h <7> <6> <5> <4:0> 16h <7:0> 17h <7:0> 18h <7> <6:4> <3:0> 19h <7:5>
remarks f or test 0 0 BW det. threshold setting : [0] of f , [1] 16mV, [2] 32mV, [3] 64mV 0 0 00h 00h Threshold control of ident judgment of sub picture decoder Sub picture read mode : [0] pixel based, [1] H based 0 0 37h Sub picture horizontal display pixel 44h Sub picture v ertical display line number 1Eh Sub picture horizontal capture position (coarse) 0h 0h Sub picture horizontal capture position (f ine) 0h 0h Sub picture C-sy nc input mask period : [0] 48us, [1] 44us, [2] 53us, [3] of f 29h Sub picture sample start line 0 0 f or test : 0 set only 0 f or test : 0 set only 0 0 0 f or test : 0 set only 11h Data slicer line selection 40h Data slicer start bit detection parameter Data slicer data slice parameter 82h 0 0h 0 0h 0h 0h 0 0h 0h 0h 0h 0h 0h 0 Frame Frame Frame Frame data data data data independent independent independent independent control : [0] disable, [1] enable B-Y data setting Y data setting R-Y data setting
0h <4> HPFOFF 0 <3:0> FREE_RUN_ADJ<3:0> 0h 1Ah <7:0> SUB_PALM_JDGE<7:0> 0h 0h 1Bh <7:6> EXPORT<1:0> 0h INV_UV <5> AFC_OFF 0h <4> 0h <3:0> HADJ<3:0> PINOE 1Ch <7> 0 <6:0> V_DAC<6:0> 0h 1Dh <7:0> PINOE<7:0> 1Eh <7:0> 1Fh <7:6> <5> <4> <3> <2> <1> <0> 20h <7:6> <5> <4> <3> <2> <1> <0> 21h <7:0> 22h <7:0> 23h <7:0> SYSTEM_STATE<1:0> MAIN_PALN SUB_UNLOCK SUB_PALN RDOF MAIN_BW WDOF NOISE<1:0> WDOF EDS_ACK2 EDS_ACK1 SIGNAL_OK READ_REQB READ_REQA PDB<15:8> PDB<7:0> PDA<15:8>
Sub picture Y output HPF : [0]on, [1]of f Frequency adjustment control when f ree run mode (2's comp)
Parameter setting f or PAL-M judgment Ext. port (7 pin) : [0]"0" output, [1]"1" output [2or3] Sub BGP Inv ert U, V output v alue : [0] normal, [1] inv ert Sub picture AFC : [0] on, [1] of f Parameter setting f or PAL-M judgment f or test 32h Sub picture V or B DAC output amplitude control E6h f or test No assignment Color state : [0] NTSC, [1] PAL-M, [2] PAL-N, [3]N.A.(Read only ) Main is : [0] not PAL-N, [1] PAL-N (Read only ) VCXO is : [0] Lock, [1] Unlock (Read only ) Sub is : [0] not PAL-N, [1] PAL-N (Read only ) Main picture V sy nc is : [0] present, [1] not present (Read only ) Test use; Alway s '1' when 10h<5:4> = "00" (Read only ) Sub picture V sy nc is : [0] present, [1] not present (Read only ) Test use (Read only ) Sub picture v ertical sy nc detection (Read only ) EDS data f lag of ev en f ield : [0] no EDS, [1] EDS (Read only ) EDS data f lag of odd f ield : [0] no EDS, [1] EDS (Read only ) Test use (Read only ) Read request of ev en f ield : [0] no, [1] requesting (Read only ) Read request of odd f ield : [0] no, [1] requesting (Read only ) Ev en f ield Sliced data upper 8 bit (Read only ) Ev en f ield Sliced data lower 8 bit (Read only ) Odd f ield Sliced data upper 8 bit (Read only ) Odd f ield Sliced data lower 8 bit (Read only )
24h <7:0> PDA<7:0>
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MITSUBISHI DIGITAL TV ICs
M65665SP/FP
PICTURE-IN-PICTURE SIGNAL PROCESSING
The relation of input signal 32-pin (Main-HD) and 33-pin (Main-VD) is shown below prohibition time of changing 33-pin signal
0
32-pin input
(Main-HD)
33-pin input
-10usec (Main-VD) [Even to Odd]
33-pin input
+10usec
(Main-VD) [Odd to Even]
+21.75usec
+41.75usec +53.5usec
20us
20us
20us
20us
20us
20us
VD input 4H 1H end of vertical equalization pulse
37.5us 20us 20us 20us 20us 20us 20us
VD input
Driv ing Method and Operating Specif ication f or Serial Interf ace Data
(1) Serial data transmission completion and start A low-to-high transition of the DATA (serial data) line while the CLK (serial clock) is high, that completes the serial transmission and makes the bus free. A high-to-low transition of the DATA line while the CLK is high, that starts the serial transmission and waits for the following CLK and DATA inputs. (2) Serial data transmission The data are transmitted in the most significant bit (MSB) first by one-byte unit on the DATA line successively. One-byte data transmission is completed by 9 clock cycles, the former 8 cycles are for address/data and the latter one is for acknowledge detection. (In reading state, ACK is 'H' under these two conditions ; 1) the coincidence of two address data for the address data transmission, 2) the completion of 8-bit setting data transfer. In writing state, ACK is 'H' with the address coincidence and ACK is 'L' for detecting acknowledge input from the master (micro processor) after sending 8-bit setting data.) For address/data transmission, DATA must change while CLK is 'L'. (The data change while CLK is 'H' or the simultaneous change of CLK and DATA, that will be a false operation because of undistinguished condition from the completion/start of serial data transfer). After the beginning of serial data transmission, the total number of data bytes that can be transferred are not limited. (3) The byte format of data transmission (The sequence of data transmission) a. The byte format during data setting to M65665FP are shown as follows. In right after the forming of serial data transmitting state, the slave address 24h (00100100b) is transferred. Afterwards, the internal register address (1 byte) and setting data (by 1 byte unit) are transferred successively. Several bytes of setting data can be handled in the one transmission. In this operation, the setting data are written into the address register whose address is increased one in initially transferred internal register address. b. The byte format during data reading from M65665FP are shown as follows. Before data reading from M65665FP, whose internal address need to be set by the data reading/transmitting. After the data reading/transmitting, the operation of "serial data transmission completion and start" (described in (1)) is necessary. Continuously, the slave address 25h (00100101b) is sent, and then the inverted read out data are available on ACK. Several bytes of writing data can be handled in the one transmission, too. In this operation, the setting data also are written into the address register whose address is increased one in initially transferred internal register address.
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MITSUBISHI DIGITAL TV ICs
M65665SP/FP
PICTURE-IN-PICTURE SIGNAL PROCESSING
(1) The writing operation of the setting data (AAh) into M65665FP internal address of 00h
Confirmation of bus free (DATA='H')
Transmission Activation
yes S 24h A 00h A AAh A D E
no
is applied on CLk for the release of output state S : Operation of serial transmission start A : Acknowledge detection D : Dummy clock feed for the release of acknowledge output state E : Operation of serial transmission completion
(2) The writing operation of the setting data (FFh, 80h, EEh) into M65665FP internal address of 04h ~ 06h
Confirmation of bus free (DATA='H')
Transmission Activation
yes S 24h A 04h A FFh A 80h A EEh A D E
no
is applied on CLk for the release of output state
(3) The reading operation of the setting data from M65665FP internal address of 00h
Transmission Activation
Confirmation of bus free (DATA='H')
yes S 24h A 00h A D E S 25h A $$h A'
no
is applied on CLk for the release of output state
A' : Bus free operation by the master (micro processor)
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MITSUBISHI DIGITAL TV ICs
M65665SP/FP
PICTURE-IN-PICTURE SIGNAL PROCESSING
(4) The reading operation of the setting data from M65665FP internal address of 04h ~ 06h
Confirmation of bus free (DATA='H')
Transmission Activation
yes S 24h A 04h A D E S 25h A $$h A" $$h A" $$h A'
no
is applied on CLk for the release of output state
A" : Output 'L' operation by the master (micro processor)

1 2 3 4 5 6 7 8 9 1
SCL (4 pin)
SDA (3 pin)
Bit7 (MSB)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 (LSB)
ACK Detec.
Bit7 (MSB)
SDA (Read data) (3 pin)
Bit7 (MSB)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 (LSB)
Bit7 (MSB)
ACK (2 pin)
ACK (Read data) (2 pin)
Bit7 (MSB)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 (LSB)
Bit7 (MSB)
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42P4B
Plastic 42pin 600mil SDIP
Weight(g) 4.1 Lead Material Alloy 42/Cu Alloy
EIAJ Package Code SDIP42-P-600-1.78
JEDEC Code -
42 22
E
e1
c
DETAILED DIAGRAM OF PACKAGE OUTLINE
L
A
e b1
b
b2
A1
A2
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21
1
Symbol
D
PICTURE-IN-PICTURE SIGNAL PROCESSING
MITSUBISHI DIGITAL TV ICs
M65665SP/FP
SEATING PLANE
A A1 A2 b b1 b2 c D E e e1 L
Dimension in Millimeters Min Nom Max - - 5.5 0.51 - - - 3.8 - 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 36.5 36.7 36.9 12.85 13.0 13.15 - 1.778 - - 15.24 - 3.0 - - 0 - 15
13
42P2R-A
Plastic 42pin 450mil SSOP
Weight(g) 0.63 Lead Material Alloy 42/Cu Alloy e b2
22
EIAJ Package Code SSOP42-P-450-0.80
JEDEC Code -
42
HE
E
e1
F Symbol
21
Recommended Mount Pad
L1
c Detail F
L
MITSUBISHI ELECTRIC
A A2 A1 b A A1 A2 b c D E e HE L L1 y b2 e1 I2
1
D
PICTURE-IN-PICTURE SIGNAL PROCESSING
MITSUBISHI DIGITAL TV ICs
M65665SP/FP
e
y
Dimension in Millimeters Min Nom Max - - 2.4 0.05 - - - 2.0 - 0.35 0.4 0.5 0.13 0.15 0.2 17.3 17.5 17.7 8.2 8.4 8.6 - 0.8 - 11.63 11.93 12.23 0.3 0.5 0.7 - 1.765 - - - 0.15 0 - 10 - 0.5 - - 11.43 - - 1.27 -
I2
14
MITSUBISHI DIGITAL TV ICs
M65665SP/FP
PICTURE-IN-PICTURE SIGNAL PROCESSING
Keep safety first in your circuit designs! lMitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials lThese materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. lMitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. lAll information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com). lWhen using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. lMitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. lThe prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. lIf these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. lPlease contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
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